Description
Since the 1970s, the complexity of systems on a chip has grown significantly. In order to improve system performance, manufacturers are integrating an increasing number of heterogeneous components on a single silicon chip. The incorporation of these components renders SoCs highly versatile yet significantly complex. Their multipurpose nature makes them suitable for use in a variety of domains, including mobile telephony, informatics, military applications, and cloud computing. SoCs process personal data (such as contacts, health information, and credit card details) and also control critical systems (such as autonomous vehicles). This raises questions about the safety of these systems. SoCs represent a significant vulnerability for attackers seeking to steal critical information or inflict damage to the system. Inadvertent vulnerabilities introduced during the design phase provide an avenue for these attacks. Such vulnerabilities frequently arise from enhancements made to boost system performance. Given that security is often an afterthought in architectural design, it is not a comprehensive solution to all potential attacks. In this talk, we will emphasize the need to reverse the historical trend of designing integrated circuits without security as a primary consideration. We will then present a heterogeneous secure-by-design SoC architecture called TrustSoC.
Practical infos
Next sessions
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HDL simulation for Masked Software Verification
Speaker : Quentin Meunier - Sorbonne Univ. Lip6
Masking is a countermeasure against Side-Channel Attacks (SCA) that aims to ensure that intermediate computations in an algorithm have secret-independent distributions through the use of random variables. This theoretically prevents SCAs, as power consumption is directly linked to the values manipulated by the program or hardware device. Designing a masking scheme is often non-trivial, and a[…]-
SemSecuElec
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Side-channel
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Étude, caractérisation et détection de verrouillage d'anneaux oscillants utilisés dans les générateurs de nombres aléatoires.
Speaker : Eloise Delolme - LabHC
Les générateurs de nombres aléatoires matériels basés sur des oscillateurs en anneau (RO-TRNGs) exploitent le jitter d’horloge comme source d’aléa afin de produire des séquences de bits aléatoires. Parmi ces architectures, le MURO-TRNG repose sur un modèle stochastique complexe qui suppose notamment l’indépendance des oscillateurs. Toutefois, dans la pratique, les oscillateurs en anneau sont[…]-
SemSecuElec
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TRNG
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Chamois: Formally verified compilation for optimisation and security
Speaker : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
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Fault injection
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Formal methods
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Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Speaker : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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