Description
Two major changes are currently taking place in the embedded processor ecosystem: open source with the RISC-V instruction set, which could replace the ARM one, and post-quantum cryptography (PQC), which could replace classic asymmetric cryptography algorithms to resist quantum computers.
In this context, this thesis investigates the improvement of embedded processor performance, generally for generic applications and more specifically for PQC-related applications. To this end, a model-driven design method is proposed.
More specifically, this work focuses on in-order processors with out-of-order execution completion. We worked on the open source CVA6 processor, maintained by the OpenHW Foundation, to improve the performance of an existing processor and share our modifications.
The first contribution is the creation of a model of CVA6 performance, cycle-accurate and easier to modify than the hardware description of this processor. This model allows a quick design space exploration and thus to refine the microarchitectural specifications. Once this step is complete, these specifications are implemented in the processor pipeline using the model as a reference to ensure the new pipeline meets performance expectations.
Applying this method has led to an improvement in the performance of the CVA6 processor, especially with the creation of a superscalar pipeline, delivering an average gain of 30% on a set of benchmarks including CoreMark, Dhrystone and the Embench suite. These modifications have been integrated into the official CVA6 repository.
Finally, this same method is used to the accelerate PQC execution in this embedded processor by implementing the support for new instructions dedicated to accelerating the NTT functions of the ML-DSA signature algorithm into its superscalar pipeline. This results in a performance gain of a factor of 5.
This thesis thus demonstrates the value of model-driven processor design.
Autre
Présentation en Français (slides en Anglais)
Talk in French (slides in English)
Practical infos
Next sessions
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Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Speaker : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Onysis: A secure European SoC FPGA
Speaker : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
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Using High Level Profiling Data to Early Assess the Fault Tolerance of Complex Digital Components
Speaker : Luc NOIZETTE - Nuclétudes (filiale Ariane group)
This presentation outlines an innovative methodology for estimating the fault tolerance of complex components based on application profiling obtained using a high-level virtual platform. A derating factor, derived exclusively from profiling metrics (e.g., lifetime in memory and registers), is calibrated using a reliability dataset collected from a set of benchmarks. Applying it to test softwares[…]-
SemSecuElec
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Fault injection
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