Table of contents

Description

Embedded electronic systems and their associated softwares are used in an always increasing number of daily life, industrial and government applications. The security of these systems is a major societal, economic and sovereignty issue. This leads to increasingly activities in research and development by scientists, industry and government services, and especially around the region around Rennes.

The topics that will be discussed during the seminar address the study, the analysis, the performance and security evaluation, the validation, and regulatory aspects of all components of secure embedded electronic systems. All these points will be addressed both at theoretical and experimental levels. Among the discussed topics, one can find: basic elements and components in electronic circuits (FPGA, ASIC, smart-cards, micro-controller), associated softwares, cryptographic primitives, crypto-processors and accelerators, secure storage, secure communication on chip, etc. One can also find secure architecture design, hardware/software co-design, performances analysis, security modules (active and passive countermeasures, secure test systems, secure memories, secure communication on chip, etc.), side channel attacks, fault injection attacks, methods and tools for reverse engineering, CAD tools and formal tools for electronic (for design or test), etc.

  • The scientific board is in charge of the organization and the program of the seminar.
    Its members are:

A seminar session will include two 45-minute talks followed by questions. The complete duration (talk + questions) for each presenter will be 1 hour.
If needed, the scientific committee may propose two short 25-minute talks instead of one 45-minute talk.
People attending to this seminar may have very different backgrounds. Then, it is required that the presenter motivates her/his work and provides explanations in a simple and clear language.

Practical infos

Next sessions

  • Sécurité physique du mécanisme d'encapsulation de clé Classic McEliece

    • March 20, 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Brice Colombier - Laboratoire Hubert Curien, Université Jean Monnet, Saint-Étienne

    Le mécanisme d'encapsulation de clé Classic McEliece faisait partie des candidats toujours en lice au dernier tour du processus de standardisation de la cryptographie post-quantique initié par le NIST en 2016. Fondé sur les codes correcteurs d'erreurs, en particulier autour du cryptosystème de Niederreiter, sa sécurité n'a pas été fondamentalement remise en cause. Néanmoins, un aspect important du[…]

    • SemSecuElec

    • Implementation of cryptographic algorithm

  • Double Strike: Breaking Approximation-Based Side-Channel Countermeasures for DNNs

    • March 20, 2026 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Lorenzo CASALINO - CentraleSupélec

    Deep neural networks (DNNs) undergo lengthy and expensive training procedures whose outcome - the DNN weights - represents a significant intellectual property asset to protect. Side-channel analysis (SCA) has recently appeared as an effective approach to recover this confidential asset of DNN implementations. Ding et al. (HOST’25) introduced MACPRUNING, a novel SCA countermeasure based on pruning,[…]

    • SemSecuElec

    • Side-channel

  • Protection des processeurs modernes face à la vulnérabilité Spectre

    • April 24, 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Herinomena ANDRIANATREHINA - Inria

    Dans la quête permanente d'une puissance de calcul plus rapide, les processeurs modernes utilisent des techniques permettant d'exploiter au maximum leurs ressources. Parmi ces techniques, l'exécution spéculative tente de prédire le résultat des instructions dont l'issue n'est pas encore connue, mais dont dépend la suite du programme. Cela permet au processeur d'éviter d'être inactif. Cependant,[…]

    • SemSecuElec

    • Micro-architectural vulnerabilities

  • Post-Quantum Cryptography Accelerated by a Superscalar RISC-V Processor

    • April 24, 2026 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Côme Allart - Inria

    Two major changes are currently taking place in the embedded processor ecosystem: open source with the RISC-V instruction set, which could replace the ARM one, and post-quantum cryptography (PQC), which could replace classic asymmetric cryptography algorithms to resist quantum computers.In this context, this thesis investigates the improvement of embedded processor performance, generally for[…]

    • SemSecuElec

    • Implementation of cryptographic algorithm

  • Chamois: Formally verified compilation for optimisation and security

    • June 26, 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : David MONNIAUX - CNRS - Verimag

    Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]

    • SemSecuElec

    • Fault injection

    • Formal methods

  • Securing processor's microarchitecture against SCA in a post-quantum cryptography setting

    • October 16, 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Vincent MIGLIORE - LAAS-CNRS

    Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]

    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities

Previous session

ML-Based Hardware Trojan Detection in AI Accelerators via Power Side-Channel Analysis

  • January 16, 2026 (11:00 - 12:00)

  • Inria Center of the University of Rennes - Espace de conférences

Speaker : Yehya NASSER - IMT Atlantique

Our work discusses the security risks associated with outsourcing AI accelerator design due to the threat of hardware Trojans (HTs), a problem traditional testing methods fail to address. We introduce a novel solution based on Power Side-Channel Analysis (PSCA), where we collect and preprocess power traces by segmenting them and extracting features from both time and frequency domains. This[…]

  • SemSecuElec

  • Side-channel

  • Machine learning

  • Hardware trojan

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