Description
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks designed not to expose the most prominent vulnerability, i.e. transition leakage. This work is then put into perspective with post-quantum cryptography (in particular code-based) that open some new interesting perspectives for design space exploration by closely link leakage to the security provided by underlying hard mathematical problems.
Autre
Présentation en Anglais (slides en Anglais)
Talk in English (slides in English)
Practical infos
Next sessions
-
Onysis: A secure European SoC FPGA
Speaker : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
-