Description
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.
In the process, it is possible that the compiler used introduces bugs, or removes countermeasures seen as redundant by the optimisations.
CompCert is a formally verified C compiler meant for safety-critical applications. It applies only a moderate amount of optimizations and lacks optimization and security features available in mainstream compilers.
Chamois is an improved version of CompCert:
- many more optimizations
- security features such as return address authentication, stack canaries, landing pads
https://gricad-gitlab.univ-grenoble-alpes.fr/certicompil/Chamois-CompCert
Based on Chamois, we propose Chamois-Arsene, which can introduce control-flow integrity countermeasures and protections against fault attacks, with mathematical proofs and experimental analyses demonstrating the effectiveness of countermeasures.
https://gricad-gitlab.univ-grenoble-alpes.fr/certicompil/Chamois-Arsene
Présentation en Anglais (slides en Anglais)
Talk in English (slides in English)
Practical infos
Next sessions
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Security of Smart Dust: Robust Key Derivation for Single-Chip Systems
Speaker : Sara Faour - Inria
The Smart Dust vision seeks to enable large networks of millimeter-scale wireless sensor nodes that tightly integrate sensing, computation, communication, and power management into a single-chip device. Establishing a robust hardware root of trust for such devices remains challenging, particularly in single, low-cost chip manufacturing processes that lack embedded writable Non-Volatile Memory (NVM[…] -
Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Speaker : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Onysis: A secure European SoC FPGA
Speaker : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
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