Table of contents

  • This session has been presented June 26, 2026 (10:00 - 11:00).

Description

  • Speaker

    David MONNIAUX - CNRS - Verimag

Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.
In the process, it is possible that the compiler used introduces bugs, or removes countermeasures seen as redundant by the optimisations.

CompCert is a formally verified C compiler meant for safety-critical applications. It applies only a moderate amount of optimizations and lacks optimization and security features available in mainstream compilers.

Chamois is an improved version of CompCert:

  • many more optimizations
  • security features such as return address authentication, stack canaries, landing pads

https://gricad-gitlab.univ-grenoble-alpes.fr/certicompil/Chamois-CompCert


Based on Chamois, we propose Chamois-Arsene, which can introduce control-flow integrity countermeasures and protections against fault attacks, with mathematical proofs and experimental analyses demonstrating the effectiveness of countermeasures.

https://gricad-gitlab.univ-grenoble-alpes.fr/certicompil/Chamois-Arsene

Présentation en Anglais (slides en Anglais)
Talk in English (slides in English)

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