Description
The Smart Dust vision seeks to enable large networks of millimeter-scale wireless sensor nodes that tightly integrate sensing, computation, communication, and power management into a single-chip device. Establishing a robust hardware root of trust for such devices remains challenging, particularly in single, low-cost chip manufacturing processes that lack embedded writable Non-Volatile Memory (NVM) for secure key storage. The thesis addresses the problem of deriving long-lived cryptographic keys on single-chip devices under the assumption of powerful physical attackers without relying on process-specific NVM.
We begin by analyzing the attack surface of highly integrated single-chip devices compared with conventional board-based devices. We show how architectural differences change the feasibility and impact of physical attacks and highlight a structural constraint: many single-chip devices do not provide writable NVM. Even when NVM is available, its persistent nature makes stored keys an attractive target for physical attacks.
The thesis then investigates SRAM-based Physically Unclonable Functions (PUFs) as a candidate root of trust. By experimentally characterizing the start-up behavior of on-chip SRAM on a representative single-chip platform, we evaluate PUF properties and show that suitably chosen memory regions can provide stable and distinctive responses that are adequate for PUF-based keys. Building on this, the thesis develops the Threshold-based Majority Voting Scheme (TMVS), a lightweight stabilization scheme tailored to Smart Dust constraints, together with a two-stage extension (TS-TMVS). Both use simple majority voting decoders to eliminate noise and mitigate bias in SRAM PUF responses, while avoiding the substantial entropy loss of repetition codes and the implementation complexity of heavy error-correcting codes. They still rely on helper data stored in NVM to support key reconstruction.
Finally, the thesis proposes On-Demand Helper Data (ODHD), an NVM-free key derivation method that regenerates both helper data and secret keys reliably by incorporating a limited number of SRAM measurements into the encoding procedure. Full experimental characterization is ongoing work. Taken together, these contributions demonstrate that robust key derivation from SRAM PUFs is feasible on single-chip devices and provide a concrete path towards secure roots of trust for future Smart Dust systems.
Practical infos
Next sessions
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HDL simulation for Masked Software Verification
Speaker : Quentin Meunier - Sorbonne Univ. Lip6
Masking is a countermeasure against Side-Channel Attacks (SCA) that aims to ensure that intermediate computations in an algorithm have secret-independent distributions through the use of random variables. This theoretically prevents SCAs, as power consumption is directly linked to the values manipulated by the program or hardware device. Designing a masking scheme is often non-trivial, and a[…]-
SemSecuElec
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Side-channel
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Étude, caractérisation et détection de verrouillage d'anneaux oscillants utilisés dans les générateurs de nombres aléatoires.
Speaker : Eloise Delolme - LabHC
Les générateurs de nombres aléatoires matériels basés sur des oscillateurs en anneau (RO-TRNGs) exploitent le jitter d’horloge comme source d’aléa afin de produire des séquences de bits aléatoires. Parmi ces architectures, le MURO-TRNG repose sur un modèle stochastique complexe qui suppose notamment l’indépendance des oscillateurs. Toutefois, dans la pratique, les oscillateurs en anneau sont[…]-
SemSecuElec
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TRNG
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Chamois: Formally verified compilation for optimisation and security
Speaker : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
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Fault injection
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Formal methods
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Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Speaker : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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