Description
Masking is a countermeasure against Side-Channel Attacks (SCA) that aims to ensure that intermediate computations in an algorithm have secret-independent distributions through the use of random variables. This theoretically prevents SCAs, as power consumption is directly linked to the values manipulated by the program or hardware device. Designing a masking scheme is often non-trivial, and a critical need for automated masking verification has emerged to ensure the correctness of masked implementations, both in hardware and in software.
In the first part of the presentation, I will introduce work on masking schemes verification, with a focus on the tool VerifMSI. Then, based on the observation that software implementations proven secure can still lead to observable secret leakages, the considered intermediate computations have progressively shifted closer to the hardware level. I will then present how the datapath of a processor core can be modeled to capture all relevant internal expressions that need to be verified when running masked software. Finally, I will present how this work can be extended to take as input the HDL of the processor core. The approach combines traditional HDL simulation with symbolic expression-based simulation in order to verify the absence of secret leakage on all wires of the HDL model. Comparisons with measured power traces from Cortex-M3 and Cortex-M4 cores have been performed and demonstrate the relevance of the approach.
Présentation en Français (slides en Anglais)
Talk in French (slides in English)
Practical infos
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