Description
Hardware Trojan Horses that are software-exploitable can be inserted into microprocessors, allowing attackers to run unauthorized code or escalate privileges. Additionally, it has been demonstrated that attackers could observe certain microprocessor features - seemingly unrelated to the program's execution - to exfiltrate secrets or private data. So, even devices produced in secure foundries could be vulnerable to such attacks. A promising defense strategy involves implementing Hardware Security Modules that monitor the runtime behavior of microprocessors to detect ongoing attacks. But why do we need Hardware Security Modules? Are software-based solutions not sufficient? Hardware Security Modules are essential because if attackers manage to execute malicious code, they could bypass or disable software defenses, leading to privilege escalation and other serious consequences. In contrast, hardware-based countermeasures raise the bar significantly, as modifying fabricated chips is far more difficult than compromising software, making Hardware Security Module implementations a more robust and resilient defense mechanism.
Infos pratiques
Prochains exposés
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Onysis: A secure European SoC FPGA
Orateur : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
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Using High Level Profiling Data to Early Assess the Fault Tolerance of Complex Digital Components
Orateur : Luc NOIZETTE - Nuclétudes (filiale Ariane group)
This presentation outlines an innovative methodology for estimating the fault tolerance of complex components based on application profiling obtained using a high-level virtual platform. A derating factor, derived exclusively from profiling metrics (e.g., lifetime in memory and registers), is calibrated using a reliability dataset collected from a set of benchmarks. Applying it to test softwares[…]-
SemSecuElec
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Fault injection
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An Assessment of the Security of Reconfigurable Cloud Computing
Orateur : Russell Tessier - University of Massachusetts
In this talk, we examine efforts to protect network processing and computation in cloud-based FPGAs from hardware- and software-based attacks. FPGAs have served as integral components in cloud computing for a decade, even though commercial FPGA architectures were not designed for cloud deployment. A range of potential attacks on cloud-based FPGAs and their remediations are examined. We[…]-
SemSecuElec
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Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Orateur : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Compositional Semantics for Detection and Defense of Speculative Leaks
Orateur : Xaver Fabian - CISPA Helmholtz Center for Information Security
Speculative execution improves CPU performance but introduces vulnerabilities, known as Spectre attacks, which exploit microarchitectural side effects to leak sensitive data. Modern processors employ multiple interacting speculation mechanisms, yet existing approaches predominantly analyze them in isolation, which limits both the automated detection of complex leaks and the formal verification of[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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