Description
Masking is a countermeasure against Side-Channel Attacks (SCA) that aims to ensure that intermediate computations in an algorithm have secret-independent distributions through the use of random variables. This theoretically prevents SCAs, as power consumption is directly linked to the values manipulated by the program or hardware device. Designing a masking scheme is often non-trivial, and a critical need for automated masking verification has emerged to ensure the correctness of masked implementations, both in hardware and in software.
In the first part of the presentation, I will introduce work on masking schemes verification, with a focus on the tool VerifMSI. Then, based on the observation that software implementations proven secure can still lead to observable secret leakages, the considered intermediate computations have progressively shifted closer to the hardware level. I will then present how the datapath of a processor core can be modeled to capture all relevant internal expressions that need to be verified when running masked software. Finally, I will present how this work can be extended to take as input the HDL of the processor core. The approach combines traditional HDL simulation with symbolic expression-based simulation in order to verify the absence of secret leakage on all wires of the HDL model. Comparisons with measured power traces from Cortex-M3 and Cortex-M4 cores have been performed and demonstrate the relevance of the approach.
Présentation en Français (slides en Anglais)
Talk in French (slides in English)
Infos pratiques
Prochains exposés
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Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Orateur : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Onysis: A secure European SoC FPGA
Orateur : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
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Using High Level Profiling Data to Early Assess the Fault Tolerance of Complex Digital Components
Orateur : Luc NOIZETTE - Nuclétudes (filiale Ariane group)
This presentation outlines an innovative methodology for estimating the fault tolerance of complex components based on application profiling obtained using a high-level virtual platform. A derating factor, derived exclusively from profiling metrics (e.g., lifetime in memory and registers), is calibrated using a reliability dataset collected from a set of benchmarks. Applying it to test softwares[…]-
SemSecuElec
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Fault injection
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