Sommaire

Description

  • Orateur

    David MONNIAUX - CNRS - Verimag

Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.
In the process, it is possible that the compiler used introduces bugs, or removes countermeasures seen as redundant by the optimisations.

CompCert is a formally verified C compiler meant for safety-critical applications. It applies only a moderate amount of optimizations and lacks optimization and security features available in mainstream compilers.

Chamois is an improved version of CompCert:

  • many more optimizations
  • security features such as return address authentication, stack canaries, landing pads

https://gricad-gitlab.univ-grenoble-alpes.fr/certicompil/Chamois-CompCert


Based on Chamois, we propose Chamois-Arsene, which can introduce control-flow integrity countermeasures and protections against fault attacks, with mathematical proofs and experimental analyses demonstrating the effectiveness of countermeasures.

https://gricad-gitlab.univ-grenoble-alpes.fr/certicompil/Chamois-Arsene

Autre

Présentation en Anglais (slides en Anglais)
Talk in English (slides in English)

Infos pratiques

Prochains exposés

  • Protection des processeurs modernes face à la vulnérabilité Spectre

    • 24 avril 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : Herinomena ANDRIANATREHINA - Inria

    Dans la quête permanente d'une puissance de calcul plus rapide, les processeurs modernes utilisent des techniques permettant d'exploiter au maximum leurs ressources. Parmi ces techniques, l'exécution spéculative tente de prédire le résultat des instructions dont l'issue n'est pas encore connue, mais dont dépend la suite du programme. Cela permet au processeur d'éviter d'être inactif. Cependant,[…]

    • SemSecuElec

    • Micro-architectural vulnerabilities

  • Post-Quantum Cryptography Accelerated by a Superscalar RISC-V Processor

    • 24 avril 2026 (11:00 - 12:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : Côme Allart - Inria

    Two major changes are currently taking place in the embedded processor ecosystem: open source with the RISC-V instruction set, which could replace the ARM one, and post-quantum cryptography (PQC), which could replace classic asymmetric cryptography algorithms to resist quantum computers.In this context, this thesis investigates the improvement of embedded processor performance, generally for[…]

    • SemSecuElec

    • Implementation of cryptographic algorithm

  • Securing processor's microarchitecture against SCA in a post-quantum cryptography setting

    • 16 octobre 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : Vincent MIGLIORE - LAAS-CNRS

    Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]

    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities

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