Table of contents

  • This session has been presented May 10, 2019.

Description

  • Speaker

    Ronan Lashermes

Electromagnetic fault injection (EMFI) is a well known technique to disturb the behavior of a chip and weaken its security. These attacks are still mostly done on simple microcontrollers since the fault effects is relatively simple and understood.
Unlocking EMFI on modern System-on-Chips (SoCs), the fast and complex chips ubiquitous today, requires to understand the impact of the faults. In this paper, we target the BCM2837 SoC with four Cortex-A53 cores from ARM. We propose an experimental setup and a forensic process to create exploitable faults and assess their impact on the micro-architecture.
The observed behaviors are radically different to what was previously obtained on microcontrollers. Subsystems (L1 caches, L2 cache, memory management unit (MMU)) can be individually targeted leading to new fault models. We highlight the differences in the fault impact with or without an Operating system (OS), therefore showing the importance of the software layers in the exploitation of a fault. The complexity and speed of a SoC does not protect them against hardware attackers, quite the contrary.
After describing the effect of faults on SoC caches and MMU, we propose countermeasures to protect the system against EMFI attacks.

Practical infos

Next sessions

  • Onysis: A secure European SoC FPGA 

    • November 13, 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Adrien GRASSEIN - Nanoxplore

    Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]
    • SemSecuElec

  • Using High Level Profiling Data to Early Assess the Fault Tolerance of Complex Digital Components

    • November 13, 2026 (11:00 - 12:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Luc NOIZETTE - Nuclétudes (filiale Ariane group)

    This presentation outlines an innovative methodology for estimating the fault tolerance of complex components based on application profiling obtained using a high-level virtual platform.  A derating factor, derived exclusively from profiling metrics (e.g., lifetime in memory and registers), is calibrated using a reliability dataset collected from a set of benchmarks.  Applying it to test softwares[…]
    • SemSecuElec

    • Fault injection

  • An Assessment of the Security of Reconfigurable Cloud Computing

    • January 06, 2027 (10:00 - 11:00)

    • Laboratoire Lab-STICC - CNRS, UMR 6285, Centre de Recherche Christiaan Huygens, Rue de Saint-Maudé, Lorient, - Salle CR-204

    Speaker : Russell Tessier - University of Massachusetts

    In this talk, we examine efforts to protect network processing and computation in cloud-based FPGAs from hardware- and software-based attacks. FPGAs have served as integral components in cloud computing for a decade, even though commercial FPGA architectures were not designed for cloud deployment. A range of potential attacks on cloud-based FPGAs and their remediations are examined. We[…]
    • SemSecuElec

  • Overcoming Challenges in Advanced Application Processor Attacks Using PEM-Assisted LFI

    • January 06, 2027 (11:00 - 12:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Jean-Max Dutertre - Ecole Mines Saint Etienne

    Modern Application Processors (or SoC) are complex multi-cores devices that run application code through an operating system. Manufactured using advanced FinFET technology, they may feature billions of transistors. They also operate at clock frequencies of over 1 GHz. This complexity is often presented as a barrier against fault injection attacks. Indeed, a potential attacker, would face two main[…]
    • SemSecuElec

    • Fault injection

  • Securing processor's microarchitecture against SCA in a post-quantum cryptography setting

    • February 12, 2027 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Vincent MIGLIORE - LAAS-CNRS

    Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]
    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities

  • Compositional Semantics for Detection and Defense of Speculative Leaks

    • February 12, 2027 (11:00 - 12:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Xaver Fabian - CISPA Helmholtz Center for Information Security

    Speculative execution improves CPU performance but introduces vulnerabilities, known as Spectre attacks, which exploit microarchitectural side effects to leak sensitive data. Modern processors employ multiple interacting speculation mechanisms, yet existing approaches predominantly analyze them in isolation, which limits both the automated detection of complex leaks and the formal verification of[…]
    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities

Show previous sessions