Description
In 2017, the NIST (National Institute for Standards and Technology) started astandardization process in order to select post-quantum encryption and digital signature schemes. Among the proposed solutions, two rank-metric based encryption schemes were selected for the second round of the standardization process: ROLLOand RQC.
This raised questions about both the performance and the security of the implementations of rank-metric cryptography. While the performance has been significantly improved recently, the question of the resistance to side-channel attacks needs to be studied more deeply.
This talk will present an overview of the existing primitives in rank-based cryptography and the challenges of making a secure implementation of these primitives.
Infos pratiques
Prochains exposés
-
Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Orateur : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
-
Side-channel
-
Micro-architectural vulnerabilities
-
-
Onysis: A secure European SoC FPGA
Orateur : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
-
-
Using High Level Profiling Data to Early Assess the Fault Tolerance of Complex Digital Components
Orateur : Luc NOIZETTE - Nuclétudes (filiale Ariane group)
This presentation outlines an innovative methodology for estimating the fault tolerance of complex components based on application profiling obtained using a high-level virtual platform. A derating factor, derived exclusively from profiling metrics (e.g., lifetime in memory and registers), is calibrated using a reliability dataset collected from a set of benchmarks. Applying it to test softwares[…]-
SemSecuElec
-
Fault injection
-