592 résultats
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CHERI: Architectural Support for Memory Protection and Software Compartmentalization
Orateur : Robert Watson - University of Cambridge
CHERI is a processor architecture protection model enabling fine-grained C/C++ memory protection and scalable software compartmentalization. CHERI hybridizes conventional processor, instruction-set, and software designs with an architectural capability model. Originating in DARPA’s CRASH research program in 2010, the work has progressed from FPGA prototypes to the recently released Arm Morello[…]-
SoSysec
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SemSecuElec
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Compartmentalization
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Micro-architectural vulnerabilities
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Hardware architecture
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CHERI: Architectural Support for Memory Protection and Software Compartmentalization
Orateur : Robert Watson - University of Cambridge
CHERI is a processor architecture protection model enabling fine-grained C/C++ memory protection and scalable software compartmentalization. CHERI hybridizes conventional processor, instruction-set, and software designs with an architectural capability model. Originating in DARPA’s CRASH research program in 2010, the work has progressed from FPGA prototypes to the recently released Arm Morello[…]-
SoSysec
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SemSecuElec
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Compartmentalization
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Hardware/software co-design
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Hardware architecture
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Comprehensive Modelling of Power Noise via Gaussian Processes with Applications to True Random Number Generators
Orateur : Maciej Skorski - Laboratoire Hubert Curien
The talk examines power noise modelling through Gaussian Processes for secure True Random Number Generators. While revisiting one-sided fractional Brownian motion, we obtain novel contributions by quantifying posterior uncertainty in exact analytical form, establishing quasi-stationary properties, and developing rigorous time-frequency analysis. These results are applied to model oscillator[…]-
Cryptography
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TRNG
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Side-Channel Based Disassembly on Complex Processors: From Microachitectural Characterization to Probabilistic Models
Orateur : Julien Maillard - CEA
Side-Channel Based Disassembly (SCBD) is a category of Side-Channel Analysis (SCA) that aims at recovering information on the code executed by a processor through the observation of physical side-channels such as power consumption or electromagnetic radiations. While traditional SCA often targets cryptographic keys, SCBD focuses on retrieving assembly code that can hardly be extracted via other[…]-
SemSecuElec
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Side-channel
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Hardware reverse
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Fine-grained dynamic partitioning against cache-based side channel attacks
Orateur : Nicolas Gaudin - Trasna
The growth of embedded systems takes advantage of architectural advances from modern processors to increase performance while maintaining a low power consumption. Among these advances is the introduction of cache memory into embedded systems. These memories speed up the memory accesses by temporarily storing data close to the execution core. Furthermore, data from different applications share the[…]-
SemSecuElec
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Micro-architectural vulnerabilities
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Hardware architecture
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SoK: Security of the Ascon Modes
Orateur : Charlotte Lefevre - Radboud University
The Ascon authenticated encryption scheme and hash function of Dobraunig et al (Journal of Cryptology 2021) were recently selected as winner of the NIST lightweight cryptography competition. The mode underlying Ascon authenticated encryption (Ascon-AE) resembles ideas of SpongeWrap, but not quite, and various works have investigated the generic security of Ascon-AE, all covering different attack[…]