Description
The security of the public-key cryptography protecting today and tomorrow's communication is threatened by the advent of quantum computers. To address this challenge, post-quantum cryptography is employed to devise new quantum-resistant cryptosystems. The National Institute of Standards and Technology (NIST), which led the quantum-safe transition, has already standardized the first lattice KEM algorithm, called ML-KEM, and has recently selected HQC, a code-based KEM, as the second future standard. The relative immaturity of the current post-quantum cryptosystems encourages a crypto-agile approach, which maintains its security by adopting an easily transitions between schemes. Intelligent crypto-agility requires identifying and implementing efficient sharing strategies between operations, which is particularly challenging when considering cryptosystems belonging to different cryptographic families. Since the last HQC team update, polynomial multiplication has become the main bottleneck of the algorithm. An alternative state-of-the-art solution to replace this operation is the Frobenius Additive Fast Fourier Transform (FAFFT), an FFT-like operation applied in the binary field.
This talk presents PHOENIX, the first efficient crypto-agile hardware strategy for sharing polynomial multiplication operations in ML-KEM and HQC. Specifically, the two operations targeted by the mutualisation are the Number Theoretic Transform (NTT), for ML-KEM, and the Frobenius Additive FFT (FAFFT), for HQC. To achieve agility, PHOENIX uses a hardware design called SuperButterfly unit, which can be configured to perform all the processing elements, known as butterfly structure, contained in the selected multiplication operations.
To our knowledge, PHOENIX is the first sharing strategy proposal in lattice-code crypto-agility, and also the first existing FAFFT hardware accelerator. We demonstrate how PHOENIX can be efficiently integrated into ML-KEM and HQC at all three NIST security levels. We finally discuss the agility overhead, in terms of resource utilization, and the respective cryptosystems performance, for all the NIST security levels, using PHOENIX in a real system-on-chip FPGA scenario.
Infos pratiques
Prochains exposés
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Protection des processeurs modernes face à la vulnérabilité Spectre
Orateur : Herinomena ANDRIANATREHINA - Inria
Dans la quête permanente d'une puissance de calcul plus rapide, les processeurs modernes utilisent des techniques permettant d'exploiter au maximum leurs ressources. Parmi ces techniques, l'exécution spéculative tente de prédire le résultat des instructions dont l'issue n'est pas encore connue, mais dont dépend la suite du programme. Cela permet au processeur d'éviter d'être inactif. Cependant,[…]-
SemSecuElec
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Micro-architectural vulnerabilities
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Post-Quantum Cryptography Accelerated by a Superscalar RISC-V Processor
Orateur : Côme Allart - Inria
Two major changes are currently taking place in the embedded processor ecosystem: open source with the RISC-V instruction set, which could replace the ARM one, and post-quantum cryptography (PQC), which could replace classic asymmetric cryptography algorithms to resist quantum computers.In this context, this thesis investigates the improvement of embedded processor performance, generally for[…]-
SemSecuElec
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Implementation of cryptographic algorithm
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Chamois: Formally verified compilation for optimisation and security
Orateur : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
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Fault injection
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Formal methods
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Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Orateur : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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