Table of contents

  • This session has been presented March 27, 2009.

Description

  • Speaker

    Nele Mentens - Katholieke Universiteit Leuven

Security in embedded systems requires the choice of a suitable implementation platform. For some systems, a general purpose microprocessor satisfies the requirements, but when high performance is the main criterium, cryptographic coprocessors in hardware are indispensable. When very high performance is required or when a high volume of coprocessors is needed, ASICs (Application Specific Integrated Circuits) are chosen as implementation platforms. In this case, the reconfigurability of FPGAs (Field Programmable Gate Arrays) is only used for prototyping. However, because of the efforts of FPGA manufacturing companies, the performance gap between ASICs and FPGAs becomes smaller and smaller. FPGAs have become heterogeneous systems with a variety of dedicated resources such as multiplier blocks, DSP slices, RAM blocks,... This explains the trend that FPGAs are more and more used as end products. Following this trend, the need for specific FPGA architectures can be justified. This presentation focuses on cryptographic coprocessor design, optimized for FPGAs.

Next sessions

  • Key Attack on the ACDGV Matrix Encryption Scheme

    • September 25, 2026 (13:45 - 14:45)

    • Batiment 32A salle 15

    Speaker : Anmoal Porwal - Technical University of Munich

    I will present our key-recovery attack on the ACDGV public-key encryption scheme proposed at ASIACRYPT 2024 by Aragon, Couvreur, Dyseryn, Gaborit, and Vinçotte. The secret key is a Gabidulin code hidden by appending random rows and columns and by left- and right-multiplication with invertible matrices. Our attack exploits the resulting algebraic structure to recover an equivalent secret key. It[…]
    • Cryptography

    • Asymmetric primitive

  • Module Learning With Errors and Structured Extrapolated Dihedral Cosets

    • October 02, 2026 (13:45 - 14:45)

    • IRMAR - Université de Rennes - Campus Beaulieu Bat. 22, RDC, Rennes - Amphi Lebesgue

    Speaker : Jinwei Zheng - Télécom Paris

    The Module Learning With Errors (MLWE) problem is the fundamental hardness assumption underlying the key encapsulation and signature schemes ML-KEM and ML-DSA, which have been selected by NIST for post-quantum cryptography standardization. Understanding its quantum hardness is crucial for assessing the security of these standardized schemes.   Inspired by the equivalence between LWE and[…]
    • Cryptography

  • European Cyber Week: atelier cryptographie post-quantique

    • From November 18, 2026 to November 19, 2026 (09:00 - 18:00)

    • Couvent des jacobins, Rennes

    Dans la continuité des éditions 2021, 2022 et 2024, la DGA — en partenariat avec CREACH LABS et avec le soutien de l'ANSSI, de l'IRISA, de l'IRMAR et du Pôle d'Excellence Cyber — organise la 4e édition de l'atelier consacré à la cryptographie post-quantique dans le cadre de l'European Cyber Week 2026. Attention, il faut s'inscrire (gratuitement) au préalable — s'inscrire à la conférence Les[…]
  • Journée post-quantique du séminaire crypto

    • November 20, 2026 (09:00 - 15:00)

    • IRMAR - Université de Rennes - Campus Beaulieu Bat. 22, RDC, Rennes - Amphi Lebesgue

    Journée scientifique sur la cryptographie post-quantique dans la foulée de l'European Cyber Week avec des exposés plus techniques que ceux de l'ECW. 
Show previous sessions