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679 results
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Seminar
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Cryptography
Combining Partial Sums and FFT for the Fastest Known Attack on 6‑Round AES
Speaker : Shibam Ghosh - Inria
The partial-sums technique introduced by Ferguson et al. (2000) achieved a 6‑round AES attack with time complexity 2^{52} S‑box evaluations, a benchmark that has stood since. In 2014, Todo and Aoki proposed a comparable approach based on the Fast Fourier Transform (FFT). In this talk, I will show how to combine partial sums with FFT to get "the best of both worlds". The resulting attack on 6[…]-
Cryptography
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Seminar
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SoSysec
Malware Detection with AI Systems: bridging the gap between industry and academia
Speaker : Luca Demetrio - University of Genova
With the abundance of programs developed everyday, it is possible to develop next-generation antivirus programs that leverage this vast accumulated knowledge. In practice, these technologies are developed with a mixture of established techniques like pattern matching, and machine learning algorithms, both tailored to achieve high detection rate and low false alarms. While companies state the[…]-
SoSysec
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Intrusion detection
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Machine learning
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Seminar
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Cryptography
Design of fast AES-based Universal Hash Functions and MACs
Speaker : Augustin Bariant - ANSSI
Ultra-fast AES round-based software cryptographic authentication/encryption primitives have recently seen important developments, fuelled by the authenticated encryption competition CAESAR and the prospect of future high-profile applications such as post-5G telecommunication technology security standards. In particular, Universal Hash Functions (UHF) are crucial primitives used as core components[…]-
Cryptography
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Seminar
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SoSysec
CHERI standardization and software ecosystem
Speaker : Carl Shaw - Codasip
This talk will describe the current status of the RISC-V International standardization process to add CHERI as an official extension to RISC-V. It will then explore the current state of CHERI-enabled operating systems, toolchains and software tool development, focusing on the CHERI-RISC-V hardware implementations of CHERI. It will then go on to give likely future development roadmaps and how the[…]-
SoSysec
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SemSecuElec
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Compartmentalization
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Operating system and virtualization
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Hardware/software co-design
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Hardware architecture
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Seminar
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SoSysec
CHERI: Architectural Support for Memory Protection and Software Compartmentalization
Speaker : Robert Watson - University of Cambridge
CHERI is a processor architecture protection model enabling fine-grained C/C++ memory protection and scalable software compartmentalization. CHERI hybridizes conventional processor, instruction-set, and software designs with an architectural capability model. Originating in DARPA’s CRASH research program in 2010, the work has progressed from FPGA prototypes to the recently released Arm Morello[…]-
SoSysec
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SemSecuElec
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Compartmentalization
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Hardware/software co-design
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Hardware architecture
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Seminar
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SemSecuElec
CHERI standardization and software ecosystem
Speaker : Carl SHAW - CODASIP
This talk will describe the current status of the RISC-V International standardization process to add CHERI as an official extension to RISC-V. It will then explore the current state of CHERI-enabled operating systems, toolchains and software tool development, focusing on the CHERI-RISC-V hardware implementations of CHERI. It will then go on to give likely future development roadmaps and how the[…]-
SoSysec
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SemSecuElec
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Compartmentalization
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Micro-architectural vulnerabilities
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