Description
This talk will describe the current status of the RISC-V International standardization process to add CHERI as an official extension to RISC-V. It will then explore the current state of CHERI-enabled operating systems, toolchains and software tool development, focusing on the CHERI-RISC-V hardware implementations of CHERI. It will then go on to give likely future development roadmaps and how the CHERI ecosystem is being grown within organizations such as the CHERI Alliance.
Next sessions
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ML-Based Hardware Trojan Detection in AI Accelerators via Power Side-Channel Analysis
Speaker : Yehya NASSER - IMT Atlantique
Our work discusses the security risks associated with outsourcing AI accelerator design due to the threat of hardware Trojans (HTs), a problem traditional testing methods fail to address. We introduce a novel solution based on Power Side-Channel Analysis (PSCA), where we collect and preprocess power traces by segmenting them and extracting features from both time and frequency domains. This[…]-
SemSecuElec
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Side-channel
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Machine learning
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Hardware trojan
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