Table of contents

  • This session has been presented April 20, 2018.

Description

  • Speaker

    Vincent Grosso

Les attaques par canaux auxiliaires sont des menaces majeures contre les mises en uvre cryptographiques. Pour contrer ces attaques, le masquage est une contre-mesure populaire. Un de ces principaux avantages est de pouvoir prouver la sécurité apportée par cette contre-mesure. Ces preuves se basent sur un certain nombre d’hypothèses sur le matériel qui met en uvre le masquage. Dans cette présentation, nous allons nous intéresser à plusieurs effets mettant à mal ces hypothèses et voir leurs impacts sur la sécurité obtenue. Nous nous intéresserons aux problèmes des transitions, des glitches, du coupling et du bruit.

Practical infos

Next sessions

  • Chamois: Formally verified compilation for optimisation and security

    • June 26, 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : David MONNIAUX - CNRS - Verimag

    Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]
    • SemSecuElec

    • Fault injection

    • Formal methods

  • Security of Smart Dust: Robust Key Derivation for Single-Chip Systems

    • June 26, 2026 (11:00 - 12:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Sara Faour - Inria

    The Smart Dust vision seeks to enable large networks of millimeter-scale wireless sensor nodes that tightly integrate sensing, computation, communication, and power management into a single-chip device. Establishing a robust hardware root of trust for such devices remains challenging, particularly in single, low-cost chip manufacturing processes that lack embedded writable Non-Volatile Memory (NVM[…]
  • Securing processor's microarchitecture against SCA in a post-quantum cryptography setting

    • October 16, 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Vincent MIGLIORE - LAAS-CNRS

    Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]
    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities

  • Onysis: A secure European SoC FPGA 

    • November 13, 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Speaker : Adrien GRASSEIN - Nanoxplore

    Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]
    • SemSecuElec

Show previous sessions