Description
The main purpose of cryptography is to ensure secure communication. In order to achieve this goal, cryptographic schemes make an intensive use of random numbers. Given that the security of these schemes highly depends on these numbers, it is important to produce high-quality random numbers. Knowing that most cryptographic modules are nowadays implemented in logic devices, we investigated True Random Number Generators (TRNGs) that can be implemented in this kind of technology. Because of the critical nature of TRNGs in cryptographic schemes, their source and their quality must be evaluated in details.
Historically, TRNGS were considered as black boxes which produce sequences of random numbers. There were therefore solely evaluated using statistical tests. However, this consideration turns out to be not acceptable for security. Modern approaches (e.g. AIS 31) consist in characterizing sources of randomness and randomness extraction mechanisms.
In this talk, we will highlight the main challenges and modern approaches in TRNG security evaluation. One of these challenges is the characterization of the source of randomness. It leads us to consider various electronic noises that need to be characterized and for which, the contribution to the overall entropy need to be assessed.
Practical infos
Next sessions
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Chamois: Formally verified compilation for optimisation and security
Speaker : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
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Fault injection
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Formal methods
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Security of Smart Dust: Robust Key Derivation for Single-Chip Systems
Speaker : Sara Faour - Inria
The Smart Dust vision seeks to enable large networks of millimeter-scale wireless sensor nodes that tightly integrate sensing, computation, communication, and power management into a single-chip device. Establishing a robust hardware root of trust for such devices remains challenging, particularly in single, low-cost chip manufacturing processes that lack embedded writable Non-Volatile Memory (NVM[…] -
Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Speaker : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Onysis: A secure European SoC FPGA
Speaker : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
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