Sommaire

  • Cet exposé a été présenté le 29 novembre 2024 (11:00 - 12:00).

Description

  • Orateur

    Raphaële Milan - Université Jean Monnet Saint-Etienne, CNRS, Laboratoire Hubert Curien UMR 5516

Since the 1970s, the complexity of systems on a chip has grown significantly. In order to improve system performance, manufacturers are integrating an increasing number of heterogeneous components on a single silicon chip. The incorporation of these components renders SoCs highly versatile yet significantly complex. Their multipurpose nature makes them suitable for use in a variety of domains, including mobile telephony, informatics, military applications, and cloud computing. SoCs process personal data (such as contacts, health information, and credit card details) and also control critical systems (such as autonomous vehicles). This raises questions about the safety of these systems. SoCs represent a significant vulnerability for attackers seeking to steal critical information or inflict damage to the system. Inadvertent vulnerabilities introduced during the design phase provide an avenue for these attacks. Such vulnerabilities frequently arise from enhancements made to boost system performance. Given that security is often an afterthought in architectural design, it is not a comprehensive solution to all potential attacks. In this talk, we will emphasize the need to reverse the historical trend of designing integrated circuits without security as a primary consideration. We will then present a heterogeneous secure-by-design SoC architecture called TrustSoC.

Infos pratiques

Prochains exposés

  • Sécurité physique du mécanisme d'encapsulation de clé Classic McEliece

    • 20 mars 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : Brice Colombier - Laboratoire Hubert Curien, Université Jean Monnet, Saint-Étienne

    Le mécanisme d'encapsulation de clé Classic McEliece faisait partie des candidats toujours en lice au dernier tour du processus de standardisation de la cryptographie post-quantique initié par le NIST en 2016. Fondé sur les codes correcteurs d'erreurs, en particulier autour du cryptosystème de Niederreiter, sa sécurité n'a pas été fondamentalement remise en cause. Néanmoins, un aspect important du[…]
    • SemSecuElec

    • Implementation of cryptographic algorithm

  • Double Strike: Breaking Approximation-Based Side-Channel Countermeasures for DNNs

    • 20 mars 2026 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : Lorenzo CASALINO - CentraleSupélec

    Deep neural networks (DNNs) undergo lengthy and expensive training procedures whose outcome - the DNN weights - represents a significant intellectual property asset to protect. Side-channel analysis (SCA) has recently appeared as an effective approach to recover this confidential asset of DNN implementations. Ding et al. (HOST’25) introduced MACPRUNING, a novel SCA countermeasure based on pruning,[…]
    • SemSecuElec

    • Side-channel

  • Protection des processeurs modernes face à la vulnérabilité Spectre

    • 24 avril 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : Herinomena ANDRIANATREHINA - Inria

    Dans la quête permanente d'une puissance de calcul plus rapide, les processeurs modernes utilisent des techniques permettant d'exploiter au maximum leurs ressources. Parmi ces techniques, l'exécution spéculative tente de prédire le résultat des instructions dont l'issue n'est pas encore connue, mais dont dépend la suite du programme. Cela permet au processeur d'éviter d'être inactif. Cependant,[…]
    • SemSecuElec

    • Micro-architectural vulnerabilities

  • Post-Quantum Cryptography Accelerated by a Superscalar RISC-V Processor

    • 24 avril 2026 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : Côme Allart - Inria

    Two major changes are currently taking place in the embedded processor ecosystem: open source with the RISC-V instruction set, which could replace the ARM one, and post-quantum cryptography (PQC), which could replace classic asymmetric cryptography algorithms to resist quantum computers.In this context, this thesis investigates the improvement of embedded processor performance, generally for[…]
    • SemSecuElec

    • Implementation of cryptographic algorithm

  • Chamois: Formally verified compilation for optimisation and security

    • 26 juin 2026 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : David MONNIAUX - CNRS - Verimag

    Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]
    • SemSecuElec

    • Fault injection

    • Formal methods

Voir les exposés passés