Description
Since the 1970s, the complexity of systems on a chip has grown significantly. In order to improve system performance, manufacturers are integrating an increasing number of heterogeneous components on a single silicon chip. The incorporation of these components renders SoCs highly versatile yet significantly complex. Their multipurpose nature makes them suitable for use in a variety of domains, including mobile telephony, informatics, military applications, and cloud computing. SoCs process personal data (such as contacts, health information, and credit card details) and also control critical systems (such as autonomous vehicles). This raises questions about the safety of these systems. SoCs represent a significant vulnerability for attackers seeking to steal critical information or inflict damage to the system. Inadvertent vulnerabilities introduced during the design phase provide an avenue for these attacks. Such vulnerabilities frequently arise from enhancements made to boost system performance. Given that security is often an afterthought in architectural design, it is not a comprehensive solution to all potential attacks. In this talk, we will emphasize the need to reverse the historical trend of designing integrated circuits without security as a primary consideration. We will then present a heterogeneous secure-by-design SoC architecture called TrustSoC.
Infos pratiques
Prochains exposés
-
Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Orateur : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
-
Side-channel
-
Micro-architectural vulnerabilities
-
-
Onysis: A secure European SoC FPGA
Orateur : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
-
-
Using High Level Profiling Data to Early Assess the Fault Tolerance of Complex Digital Components
Orateur : Luc NOIZETTE - Nuclétudes (filiale Ariane group)
This presentation outlines an innovative methodology for estimating the fault tolerance of complex components based on application profiling obtained using a high-level virtual platform. A derating factor, derived exclusively from profiling metrics (e.g., lifetime in memory and registers), is calibrated using a reliability dataset collected from a set of benchmarks. Applying it to test softwares[…]-
SemSecuElec
-
Fault injection
-