Description
Embedded devices face software and physical fault injections to either extract or tamper with code in memory. The code execution and code intellectual property are threatened. Some existing countermeasures provide Control Flow Integrity (CFI) extended with the confidentiality and integrity of the instructions by chaining all of them through a cryptographic encryption primitive. While tampering with instructions in memory is prevented, fault injection attacks can still target the microarchitecture. In this talk, we introduce a new chained instruction encryption scheme with associated control signals, to provide additional authenticity and integrity properties down to the control signals of the microarchitecture’s pipeline. The instructions are stored encrypted in memory. At runtime, prior to being executed, the fetched instructions are decrypted depending on the control signals in the pipeline and all the previously decrypted instructions. In case of fault injections, targeting either instructions or control signals, the decryption process fails and generates random instructions, instead of the original ones. This quickly leads to an invalid instruction exception: the fault attack is thwarted. Our scheme was implemented on FPGA, into the 4-stage pipeline of the RISC-V cv32e40p core, using Ascon for encryption/decryption.
Infos pratiques
Prochains exposés
-
Protection des processeurs modernes face à la vulnérabilité Spectre
Orateur : Herinomena ANDRIANATREHINA - Inria
Dans la quête permanente d'une puissance de calcul plus rapide, les processeurs modernes utilisent des techniques permettant d'exploiter au maximum leurs ressources. Parmi ces techniques, l'exécution spéculative tente de prédire le résultat des instructions dont l'issue n'est pas encore connue, mais dont dépend la suite du programme. Cela permet au processeur d'éviter d'être inactif. Cependant,[…]-
SemSecuElec
-
Micro-architectural vulnerabilities
-
-
Post-Quantum Cryptography Accelerated by a Superscalar RISC-V Processor
Orateur : Côme Allart - Inria
Two major changes are currently taking place in the embedded processor ecosystem: open source with the RISC-V instruction set, which could replace the ARM one, and post-quantum cryptography (PQC), which could replace classic asymmetric cryptography algorithms to resist quantum computers.In this context, this thesis investigates the improvement of embedded processor performance, generally for[…]-
SemSecuElec
-
Implementation of cryptographic algorithm
-
-
Chamois: Formally verified compilation for optimisation and security
Orateur : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
-
Fault injection
-
Formal methods
-
-
Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Orateur : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
-
Side-channel
-
Micro-architectural vulnerabilities
-