Description
Embedded devices face software and physical fault injections to either extract or tamper with code in memory. The code execution and code intellectual property are threatened. Some existing countermeasures provide Control Flow Integrity (CFI) extended with the confidentiality and integrity of the instructions by chaining all of them through a cryptographic encryption primitive. While tampering with instructions in memory is prevented, fault injection attacks can still target the microarchitecture. In this talk, we introduce a new chained instruction encryption scheme with associated control signals, to provide additional authenticity and integrity properties down to the control signals of the microarchitecture’s pipeline. The instructions are stored encrypted in memory. At runtime, prior to being executed, the fetched instructions are decrypted depending on the control signals in the pipeline and all the previously decrypted instructions. In case of fault injections, targeting either instructions or control signals, the decryption process fails and generates random instructions, instead of the original ones. This quickly leads to an invalid instruction exception: the fault attack is thwarted. Our scheme was implemented on FPGA, into the 4-stage pipeline of the RISC-V cv32e40p core, using Ascon for encryption/decryption.
Infos pratiques
Prochains exposés
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Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Orateur : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Onysis: A secure European SoC FPGA
Orateur : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
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Using High Level Profiling Data to Early Assess the Fault Tolerance of Complex Digital Components
Orateur : Luc NOIZETTE - Nuclétudes (filiale Ariane group)
This presentation outlines an innovative methodology for estimating the fault tolerance of complex components based on application profiling obtained using a high-level virtual platform. A derating factor, derived exclusively from profiling metrics (e.g., lifetime in memory and registers), is calibrated using a reliability dataset collected from a set of benchmarks. Applying it to test softwares[…]-
SemSecuElec
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Fault injection
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