Sommaire

  • Cet exposé a été présenté le 29 mars 2019.

Description

  • Orateur

    Bohan Yang

True randomness is all about unpredictability, which can neither be qualified nor quantified by examining statistics of a sequence of digits. Unpredictability is a property of random phenomena, which is measured in bits of information entropy. Application of randomness spans from art to numerical computing and system security. Random numbers enable various cryptographic algorithms, protocols and secured implementations by providing secret keys, initialization vectors, random challenges and masks. As embedded electronics continue to be integrated into our daily lives, security becomes an indispensable requirement for an embedded system. According to the renowned Kerckhoffs’ principle, a cryptographic system should be secure even if the attacker knows everything about the system, except the key. In modern computers and embedded systems, this key is usually generated by executing a True Random Number Generator. Therefore, it is essential that unpredictable random numbers are available in secure embedded systems. Unfortunately, designing a TRNG is not trivial and different from conventional digital circuit design, since most digital circuits are primarily developed to behave in a deterministic digital manner. Instead of pursuing a stable and predictable behavior of the circuit, the TRNG design aims for a stable and robust unpredictability. Producing unpredictable output is usually undesired for an integrated circuit, and is sometimes regarded as a design failure. Having mistakes or being careless at any step of the TRNG design and fabrication procedure may lead to insufficient entropy or/and a malfunctioned TRNG. A True Random Number Generator (TRNG) circuit is designed to be sensitive to a particular physical phenomenon when it is in use, and to be resistant to process variations and other unwanted random physical phenomena. In order to tackle the lack of compact and efficient TRNGs on FPGAs, we proposed a novel TRNG based on edge sampling.

Infos pratiques

Prochains exposés

  • ML-Based Hardware Trojan Detection in AI Accelerators via Power Side-Channel Analysis

    • 16 janvier 2026 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Orateur : Yehya NASSER - IMT Atlantique

    Our work discusses the security risks associated with outsourcing AI accelerator design due to the threat of hardware Trojans (HTs), a problem traditional testing methods fail to address. We introduce a novel solution based on Power Side-Channel Analysis (PSCA), where we collect and preprocess power traces by segmenting them and extracting features from both time and frequency domains. This[…]
    • SemSecuElec

    • Side-channel

    • Machine learning

    • Hardware trojan

Voir les exposés passés