PHOENIX : the first crypto-agile hardware solution for ML-KEM and HQC

The security of the public-key cryptography protecting today and tomorrow's communication is threatened by the advent of quantum computers. To address this challenge, post-quantum cryptography is employed to devise new quantum-resistant cryptosystems. The National Institute of Standards and Technology (NIST), which led the quantum-safe transition, has already standardized the first lattice KEM algorithm, called ML-KEM, and has recently selected HQC, a code-based KEM, as the second future standard. The relative immaturity of the current post-quantum cryptosystems encourages a crypto-agile approach, which maintains its security by adopting an easily transitions between schemes. Intelligent crypto-agility requires identifying and implementing efficient sharing strategies between operations, which is particularly challenging when considering cryptosystems belonging to different cryptographic families. Since the last HQC team update, polynomial multiplication has become the main bottleneck of the algorithm. An alternative state-of-the-art solution to replace this operation is the Frobenius Additive Fast Fourier Transform (FAFFT), an FFT-like operation applied in the binary field. 

This talk presents PHOENIX, the first efficient crypto-agile hardware strategy for sharing polynomial multiplication operations in ML-KEM and HQC. Specifically, the two operations targeted by the mutualisation are the Number Theoretic Transform (NTT), for ML-KEM, and the Frobenius Additive FFT (FAFFT), for HQC. To achieve agility, PHOENIX uses a hardware design called SuperButterfly unit, which can be configured to perform all the processing elements, known as butterfly structure, contained in the selected multiplication operations. 

To our knowledge, PHOENIX is the first sharing strategy proposal in lattice-code crypto-agility, and also the first existing FAFFT hardware accelerator. We demonstrate how PHOENIX can be efficiently integrated into ML-KEM and HQC at all three NIST security levels. We finally discuss the agility overhead, in terms of resource utilization, and the respective cryptosystems performance, for all the NIST security levels, using PHOENIX in a real system-on-chip FPGA scenario.