Description
The masking countermeasure constitutes a provably secure approach against side-channel attacks. Nonetheless, in the software context, the micro-architecture underlying a given CPU potentially induces information leakages undermining the masking's proven security.
In this seminar, I will present the research work developed during my Ph.D. at CEA-List in Grenoble. This work addresses, along two axes, the problem of developing practically secure masked software.
The first axis targets the automated generation of masked software resilient to transition-based leakages, putting forward the employment of register allocation and instruction scheduling to mitigate such leakages during the compilation of the masked software.
The second axis focuses on the impact of the micro-architecture on alternative types of masking, studying their potential employment as a micro-architecture-independent approach to protect software implementations against both transition-based leakages and data parallelism; this latter an unexplored topic for masked software implementations.
I will conclude the seminar highlighting key points concerning the development of practically secure masked software and potential future developments of my research work.
Prochains exposés
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Chamois: Formally verified compilation for optimisation and security
Orateur : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
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Fault injection
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Formal methods
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Security of Smart Dust: Robust Key Derivation for Single-Chip Systems
Orateur : Sara Faour - Inria
The Smart Dust vision seeks to enable large networks of millimeter-scale wireless sensor nodes that tightly integrate sensing, computation, communication, and power management into a single-chip device. Establishing a robust hardware root of trust for such devices remains challenging, particularly in single, low-cost chip manufacturing processes that lack embedded writable Non-Volatile Memory (NVM[…] -
Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Orateur : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Onysis: A secure European SoC FPGA
Orateur : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
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