Description
Electromagnetic fault injection (EMFI) is a well known technique to disturb the behavior of a chip and weaken its security. These attacks are still mostly done on simple microcontrollers since the fault effects is relatively simple and understood.
Unlocking EMFI on modern System-on-Chips (SoCs), the fast and complex chips ubiquitous today, requires to understand the impact of the faults. In this paper, we target the BCM2837 SoC with four Cortex-A53 cores from ARM. We propose an experimental setup and a forensic process to create exploitable faults and assess their impact on the micro-architecture.
The observed behaviors are radically different to what was previously obtained on microcontrollers. Subsystems (L1 caches, L2 cache, memory management unit (MMU)) can be individually targeted leading to new fault models. We highlight the differences in the fault impact with or without an Operating system (OS), therefore showing the importance of the software layers in the exploitation of a fault. The complexity and speed of a SoC does not protect them against hardware attackers, quite the contrary.
After describing the effect of faults on SoC caches and MMU, we propose countermeasures to protect the system against EMFI attacks.
Infos pratiques
Prochains exposés
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Chamois: Formally verified compilation for optimisation and security
Orateur : David MONNIAUX - CNRS - Verimag
Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]-
SemSecuElec
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Fault injection
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Formal methods
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Security of Smart Dust: Robust Key Derivation for Single-Chip Systems
Orateur : Sara Faour - Inria
The Smart Dust vision seeks to enable large networks of millimeter-scale wireless sensor nodes that tightly integrate sensing, computation, communication, and power management into a single-chip device. Establishing a robust hardware root of trust for such devices remains challenging, particularly in single, low-cost chip manufacturing processes that lack embedded writable Non-Volatile Memory (NVM[…] -
Securing processor's microarchitecture against SCA in a post-quantum cryptography setting
Orateur : Vincent MIGLIORE - LAAS-CNRS
Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]-
SemSecuElec
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Side-channel
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Micro-architectural vulnerabilities
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Onysis: A secure European SoC FPGA
Orateur : Adrien GRASSEIN - Nanoxplore
Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]-
SemSecuElec
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