Sommaire

  • Cet exposé a été présenté le 28 septembre 2018.

Description

  • Orateur

    Victor Lomné et Thomas Roche

Side-channel attacks on public-key cryptography (i.e. modular exponentiation for RSA or scalar multiplication for ECC) often boils down to distinguishing the 0s from the 1s in the binary representation of the secret exponent (resp. secret scalar).
When state-of-the-art countermeasures are implemented, this detection must be errorless: thanks to masking techniques, erroneous masked exponents (resp. masked scalars) are useless.
In 2011, Schindler and Itoh tackle this issue and propose an algorithm to recover the unmasked exponent (resp. scalar) from many erroneous masked exponents (resp. masked scalars). Schindler and Wiemers improve these results in 2014 and then in 2017.
In our talk we will introduce the context of side-channel attacks over public-key cryptography, present the results of Schindler et al. and propose improvements.

Prochains exposés

  • Chamois: Formally verified compilation for optimisation and security

    • 26 juin 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : David MONNIAUX - CNRS - Verimag

    Embedded programs (including those on smart cards) are often developed in C and then compiled for the embedded processor. Sometimes they are modified by hand to incorporate countermeasures (fault attacks, etc.), but care must be taken to ensure that this does not disrupt normal program execution and that the countermeasure is actually adequate for blocking the attacks.In the process, it is[…]
    • SemSecuElec

    • Fault injection

    • Formal methods

  • Security of Smart Dust: Robust Key Derivation for Single-Chip Systems

    • 26 juin 2026 (11:00 - 12:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : Sara Faour - Inria

    The Smart Dust vision seeks to enable large networks of millimeter-scale wireless sensor nodes that tightly integrate sensing, computation, communication, and power management into a single-chip device. Establishing a robust hardware root of trust for such devices remains challenging, particularly in single, low-cost chip manufacturing processes that lack embedded writable Non-Volatile Memory (NVM[…]
  • Securing processor's microarchitecture against SCA in a post-quantum cryptography setting

    • 16 octobre 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : Vincent MIGLIORE - LAAS-CNRS

    Hardware microarchitecture is a well-known source of side-channel leakages, providing a notable security reduction of standard cryptographic algorithms (e.g. AES) if not properly addressed by software or hardware. In this talk, we present new design approaches to harden processor's microarchitecture against power-based side-channel attacks, relying on configurable and cascadable building blocks[…]
    • SemSecuElec

    • Side-channel

    • Micro-architectural vulnerabilities

  • Onysis: A secure European SoC FPGA 

    • 13 novembre 2026 (10:00 - 11:00)

    • IETR - University of Rennes - Campus de BEAULIEU - Bâtiment 11D, salle numéro 18

    Orateur : Adrien GRASSEIN - Nanoxplore

    Developed in collaboration with the DGA, the Onysis project introduces a European SoC FPGA designed to embed advanced hardware security features. This presentation will provide an overview of the Onysis architecture, focusing specifically on its native mechanisms to protect critical systems. We will detail the implementation of its integrated security subsystem, covering the secure boot sequence[…]
    • SemSecuElec

Voir les exposés passés