Description
This talk is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing. We propose here a novel hardware implementation of Miller's loop based on a pipelined Karatsuba-Ofman multiplier. Thanks to a careful choice of the mean of computing the Tate pairing and algorithms for tower field arithmetic, we manage to keep the pipeline busy. We also describe the strategies we considered to design our parallel multiplier. They are included in a VHDL code generator allowing for the exploration of a wide range of operators. Then, we sketch the architecture of two coprocessors for the Tate pairing over GF(2^m) and GF(3^m). However, a final exponentiation is still needed to obtain a unique value, which is desirable in most of the cryptographic protocols. We supplement our pairing accelerators with a coprocessor responsible for this task. An improved exponentiation algorithm allows us to save hardware resources.<br/> According to our place-and-route results on Xilinx FPGAs, our designs improve both the computation time and the area-time trade-off compared to previoulsy published coprocessors.
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