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652 results

    • Seminar

    • Cryptography

    Design of fast AES-based Universal Hash Functions and MACs

    • October 10, 2025 (13:45 - 14:45)

    • IRMAR - Université de Rennes - Campus Beaulieu Bat. 22, RDC, Rennes - Amphi Lebesgue

    Speaker : Augustin Bariant - ANSSI

    Ultra-fast AES round-based software cryptographic authentication/encryption primitives have recently seen important developments, fuelled by the authenticated encryption competition CAESAR and the prospect of future high-profile applications such as post-5G telecommunication technology security standards. In particular, Universal Hash Functions (UHF) are crucial primitives used as core components[…]

    • Cryptography

    • Seminar

    • SoSysec

    CHERI standardization and software ecosystem

    • September 12, 2025 (11:00 - 12:00)

    • Inria Centre of the University of Rennes - Room Métivier

    Speaker : Carl Shaw - Codasip

    This talk will describe the current status of the RISC-V International standardization process to add CHERI as an official extension to RISC-V. It will then explore the current state of CHERI-enabled operating systems, toolchains and software tool development, focusing on the CHERI-RISC-V hardware implementations of CHERI. It will then go on to give likely future development roadmaps and how the[…]

    • SoSysec

    • SemSecuElec

    • Compartmentalization

    • Operating system and virtualization

    • Hardware/software co-design

    • Hardware architecture

    • Seminar

    • SoSysec

    CHERI: Architectural Support for Memory Protection and Software Compartmentalization

    • September 12, 2025 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Room Métivier

    Speaker : Robert Watson - University of Cambridge

    CHERI is a processor architecture protection model enabling fine-grained C/C++ memory protection and scalable software compartmentalization. CHERI hybridizes conventional processor, instruction-set, and software designs with an architectural capability model. Originating in DARPA’s CRASH research program in 2010, the work has progressed from FPGA prototypes to the recently released Arm Morello[…]

    • SoSysec

    • SemSecuElec

    • Compartmentalization

    • Hardware/software co-design

    • Hardware architecture

    • Seminar

    • SemSecuElec

    CHERI standardization and software ecosystem

    • September 12, 2025 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Carl SHAW - CODASIP

    This talk will describe the current status of the RISC-V International standardization process to add CHERI as an official extension to RISC-V. It will then explore the current state of CHERI-enabled operating systems, toolchains and software tool development, focusing on the CHERI-RISC-V hardware implementations of CHERI. It will then go on to give likely future development roadmaps and how the[…]

    • SoSysec

    • SemSecuElec

    • Compartmentalization

    • Micro-architectural vulnerabilities

    • Seminar

    • SoSysec

    Towards privacy-preserving and fairness-aware federated learning framework

    • September 19, 2025 (11:00 - 12:00)

    • Inria Center of the University of Rennes - Petri/Turing room

    Speaker : Nesrine Kaaniche - Télécom SudParis

    Federated Learning (FL) enables the distributed training of a model across multiple data owners under the orchestration of a central server responsible for aggregating the models generated by the different clients. However, the original approach of FL has significant shortcomings related to privacy and fairness requirements. Specifically, the observation of the model updates may lead to privacy[…]

    • Cryptography

    • SoSysec

    • Privacy

    • Machine learning

    • Seminar

    • SemSecuElec

    CHERI: Architectural Support for Memory Protection and Software Compartmentalization

    • September 12, 2025 (10:00 - 11:00)

    • Inria Center of the University of Rennes - Espace de conférences

    Speaker : Robert Watson - University of Cambridge

    CHERI is a processor architecture protection model enabling fine-grained C/C++ memory protection and scalable software compartmentalization. CHERI hybridizes conventional processor, instruction-set, and software designs with an architectural capability model. Originating in DARPA’s CRASH research program in 2010, the work has progressed from FPGA prototypes to the recently released Arm Morello[…]

    • SoSysec

    • SemSecuElec

    • Compartmentalization

    • Micro-architectural vulnerabilities

    • Hardware architecture

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