Description
CHERI is a processor architecture protection model enabling fine-grained C/C++ memory protection and scalable software compartmentalization. CHERI hybridizes conventional processor, instruction-set, and software designs with an architectural capability model. Originating in DARPA’s CRASH research program in 2010, the work has progressed from FPGA prototypes to the recently released Arm Morello prototype processor and SoC implementing CHERI principles, Microsoft’s CHERIoT microcontroller, and multiple commercial products shipping from 2025 onwards. This talk will introduce the design principles of CHERI, explain how software works on the platform, and explore the large-scale evaluation case studies based on tens of millions of lines of open-source code. It will conclude by exploring future research directions as well as in-progress transition into industrial use.
Prochains exposés
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Vers l’émergence d’un droit européen pour la Blockchain : Une approche sous l’angle de la Privacy et de l’encadrement des crypto-actifs
Orateur : Damien Franchi - Univ Rennes, IODE
La Blockchain, technologie derrière Bitcoin, fait l’objet d’un encadrement juridique de plusen plus important, en particulier de la part de l’Union européenne. Curieusement, le mot« Blockchain » n’apparaît pas dans les textes l’encadrant. Les expressions « technologie deregistres distribués » (Distributed ledger technology, DLT), ou, parfois, « registreélectronique » lui sont plutôt privilégiées.[…]-
SoSysec
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Law
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Blockchain and digital currencies: between European regulation and technological challenges
Orateur : Loïc Miller - CentraleSupélec
As the European Union develops a legal framework for crypto-assets and data protection, the technological question underlying the emergence of a genuine digital currency remains open. Blockchain today stands as an interdisciplinary field of study at the crossroads of computer science, economics, and law. This presentation will place the ongoing regulatory framework in perspective with the[…]-
SoSysec
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Distributed systems
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Hardware-Software Co-Designs for Microarchitectural Security
Orateur : Lesly-Ann Daniel - EURECOM
Microarchitectural optimizations, such as caches and speculative out-of-order execution, are essential for achieving high performance. However, these same mechanisms also open the door to attacks that can undermine software-enforced security policies. The current gold standard for defending against such attacks is the constant-time programming discipline, which prohibits secret-dependent control[…]-
SoSysec
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Hardware/software co-design
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Micro-architectural vulnerabilities
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