Description
When designing an electronic device, security is a key aspect to consider. There are numerous vulnerability sources and exploitation methods.
In particular, we are interested in fault injection. These attacks consist of perturbing some of the circuit signals (such as the power supply) to modify their behaviour.
Understanding the impact of faults on an integrated circuit is necessary to design effective countermeasures or attacks. Electromagnetic fault injection impacts several signals at once, so its study can be complex.
This thesis aims to study one particular effect of electromagnetic faults: the synchronous clock glitch. This glitch has been used successfully to bypass security measures.
However, an in-depth analysis has never been explored. First, we explore its effect on registers and their sampling, which allows us to identify a new fault model.
We then focus on the effect of the glitch on the microarchitecture. Our goals are multiple: to establish the link between the injection parameters and the various effects observed,
to identify the vulnerable parts of the processor, and to establish the link with the low-level fault model.
These two contributions will improve our understanding of the effects of fault injection, particularly electromagnetic faults, at various levels of abstraction.
PhD directed by Mr Olivier SENTIEYS
The Jury
- BEROULLE Vincent, Professeur, Grenoble INP-UGA Esisar, LCIS, Valence
- MENDEZ-REAL Maria, Chaire de Professeur Junior, Université de Bretagne-Sud, Lab-STICC, Lorient
- CLEDIERE Jessy, Directeur de Recherche, CEA Leti, Grenoble
- DUTERTRE Jean-Max, Professeur, Ecole des Mines de Saint-Etienne, Gardanne
The advisors
- SENTIEYS Olivier, Professeur, Université de Rennes, IRISA, Inria
- LASHERLES Ronan, Ingénieur de Recherche, Inria, Rennes
- DAFALI Rachid, Expert sécurité matérielle, DGA MI
- BOUFFARD Guillaume, Expert sécurité des systèmes embarqués, ANSSI